The present invention relates to composite PNP transistors, and more particularly to composite transistors using NPN transistors and p-channel junction field effect transistors.
Standard bipolar integrated circuit processes provide high speed vertical NPN transistors that are fabricated by diffusing a p-type base region into an n-type epitaxial layer and subsequently diffusing an n-type emitter region into the p-type base region. However, the standard bipolar integrated circuit process usually provides only low speed lateral PNP transistors wherein the n-type base region is formed by lithographic means or low speed substrate PNP transistors wherein the collector is the p-type substrate. Although these low speed transistors are deemed to be "complementary" to the vertical NPN transistors because they may used together in certain limited design configurations, they are not strictly complementary to the NPN transistors in the sense that the saturation current, I.sub.S, of the emitter base junction of the transistors is not equal. Therefore, there are disparities in the current-voltage characteristics between the PNP and NPN transistors making it impossible to use certain desirable complementary design configurations.
Some bipolar integrated circuits provide a p-channel JFET (junction field effect transistor) that, while not having the frequency performance of the vertical NPN transistor, is far superior to the lateral PNP transistor. However, these devices are also not complementary because the saturation current and current-voltage characteristics differ from the vertical NPN transistor. Therefore what is desired is a composite PNP transistor that maintains the high speed of the JFET yet is complementary to the current-voltage characteristics of the vertical NPN transistor.